1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to signal interpolation.
2. Discussion of Related Art
There are a variety of applications that may benefit from the use of a signal interpolator or other circuitry that provides phase-stepped signal edges. One such application is integrated circuit device testing.
For example, to reduce test costs associated with high frequency chip interfaces, a self-test technique referred to as I/O loopback may be used to test I/O timings. In an exemplary I/O loopback testing approach, the ability of an input buffer to correctly latch data driven by an output buffer on the same chip is measured while the timing of associated signals is adjusted to determine the passing range for the I/O buffer. An example of an I/O loopback testing approach is described in U.S. Pat. No. 5,621,739 to Sine et al. assigned to the assignee of the present invention.
To perform I/O loopback testing, it is desirable to be able to generate half-quadrature clock phases for accurate timing measurements. If the clock signals used to perform the I/O self-test are adversely affected by process, voltage and/or temperature variations, clock jitter or other factors, testing of the I/O circuitry may be inaccurate. Inaccurate testing may result in false failures or false passes of the test, either of which may be costly to the manufacturer, the system supplier or the end user.
As a balancing factor, the circuitry that provides the variable signals used to perform such testing may not be useful during normal operation of the integrated circuit. Thus, while it is desirable to have a high level of accuracy in producing signals used for testing, it is also desirable to keep the circuit real estate and development costs relatively small.